1. Field of the Invention
The invention relates to semiconductor fabrication, and in particular the design of a mask alignment test structure for electrically measuring the alignment of superimposed elements on the surface of a semiconductor integrated circuit after processing.
2. Description of the Prior Art
Most semiconductor devices are now made by photolithographic techniques. Such techniques involve the exposure of the surface of a semiconductor body to a particular pattern, and the subsequent formation or development of that pattern into permanent form through the use of wet or dry etching techniques that create various regions and structures on the surface of the semiconductor body. As is well known in the art, photolithographic procedures require that masks be used to define those portions of the semiconductor material where various elements of semiconductor devices are to be located. Because different parts or elements of these semiconductor devices must be located at precisely defined distances from one another, it is desirable that each of the masks be used in forming the semiconductor devices be aligned with respect to one another as precisely as possible both in vertical and horizontal directions.
These operations of alignment and determining the extent of processing are done visually by an operation examining the surface of the semiconductor wafer and the mask under a microscope. The use of marks on the mask and on the wafer are known to facilitate the monitor or measure the misalignment. However, prior to the present invention, this visual measurement procedure is very time consuming and depends on the human errors. Also, a large number of measurements across the wafer as from wafer to wafer are very difficult. In large scale production processes it is also desirable to obtain a statistical base of information on the quantity and relative alignment of elements across the wafer for a large number of processed wafers.